Security researcher Christopher Domas has released a proof-of-concept project called “skitter-creek-bath-salts,” which demonstrates a vulnerability in AMD’s DRAM-controller configuration that could compromise hardware-enforced memory isolation.
This technique, tested on AMD Family 16h processors, manipulates address-translation behavior in the memory-controller layer, allowing access to data typically protected from the operating system, the kernel, and even ring-0 code.
The research specifically targets the final stage of physical memory addressing: the Memory Controller Technology/Data Controller Technology (MCT/DCT) pipeline.
While software and firmware protections generally limit access using physical addresses, the memory controller ultimately translates those addresses into DRAM coordinates such as channel, rank, bank, row, and column.
Domas’ work shows that modifying a controller register can alter this translation after higher-level protections have already enforced access controls.
New DRAM Scrambling Attack
At the core of the demonstration is a DRAM “scrambling” operation that toggles memory-controller address-remapping settings. According to the project documentation, a single configuration change can cause an address to resolve to a different physical DRAM location than what the rest of the platform expects.
This creates a temporary alternate view of memory: a protected region may remain inaccessible through its legitimate physical address, but a carefully calculated alias can access the same underlying DRAM cells while bypassing the access controls applied to the original address.
The proof of concept aims to maintain system stability by minimizing the duration spent in the altered memory state. It disables interrupts, prepares the relevant translation and cache state, changes the controller mapping, performs a targeted read or write operation, and then restores the original configuration.
While this approach is inherently fragile, it clearly illustrates how vulnerabilities below conventional memory protections can invalidate the assumptions those protections rely upon.
The project employs linear algebra and the Z3 SMT solver to reconstruct the relationship between normal and scrambled memory mappings.
Researchers gather pairs of physical addresses that resolve to the same DRAM location under different controller configurations and then solve for a translation matrix.
Once derived, this matrix serves as a conversion mechanism between a protected address and an accessible alias under the manipulated mapping. The project includes tools designed to identify aliases and read or write specified memory regions.
Domas demonstrates potential access to several highly privileged areas, including:
- AMD Platform Security Processor (PSP) memory, which encompasses memory associated with fTPM functionality.
- System Management Mode (SMM) memory, including SMI handler code that is typically protected in SMRAM.
- C6 idle-state save areas, which can store architectural processor state.
- Microcode patch storage, where a copy of loaded microcode may be preserved in DRAM during low-power CPU states.
The microcode aspect is especially noteworthy. The documentation claims that it is possible to recover the microcode patch body from a C6 save area and that the same aliasing mechanism could potentially modify that DRAM-resident copy before a core restores its state.
Scope and Impact
The available proof of concept was developed and tested specifically on AMD Family 16h systems, which are the last AMD generation for which public documentation revealed relevant DRAM-controller translation registers without indicating that they could be locked.
The research does not confirm that newer AMD processors, Intel systems, ARM devices, or RISC-V platforms are vulnerable in the same manner.
However, it raises a broader architectural concern: trusted execution technologies and firmware-protected regions ultimately rely on DRAM address translation.
If an attacker can reprogram that final translation layer, protections implemented above it may no longer align with the actual DRAM location being accessed.
For defenders, this work emphasizes the importance of locking memory-controller configurations early in the boot process, auditing firmware register controls, and treating undocumented memory-controller behavior as a potential failure in security boundaries, not just a reliability issue.
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